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32509hkim 20070522-s00003/70506hkim no.a0428-1/18 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 lc75836w overview the lc75836w is 1/4-duty general-purpose microprocessor-controlled lcd driver that can be used in applications such as frequency display in products with electronic tuning. in addition to being able to drive up to 140 segments directly, the lc75836w can also control up to 4 general-purpose output ports. features ? 1/4 duty, 1/3 bias drive (up to 140 segment can be displayed.) ? serial data input supports ccb* format communication with the system controller (support 3v operation). ? serial data control of the power-saving mode based backup function and the all segments forced off function. ? serial data control of switching between the segment output port and general-purpose output port functions. ? serial data control of the frame frequency of the common and segment output waveforms. ? either rc oscillator operating or external clock operatin g mode can be selected with the serial control data. ? high generality, since display data is displayed directly without the intervention of a decoder circuit. ? the inh pin allows the display to be forced to the off state. ? rc oscillation circuit (with external resistor and capacitor) ordering number : ENA0428a cmos ic 1/4-duty general-purpose lcd display driver ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. ? ccb is a registered trademark of semiconductor components industries, llc.
lc75836w no.a0428-2/18 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd -0.3 to +7.0 v v in 1 ce, cl, di, inh -0.3 to +7.0 input voltage v in 2 osc, v dd 1, v dd 2 -0.3 to v dd +0.3 v output voltage v out s1 to s35, com1 to com4, p1 to p4, osc -0.3 to v dd +0.3 v i out 1 s1 to s35 300 a i out 2 com1 to com4 3 output current i out 3 p1 to p4 5 ma allowable power dissipation pdmax ta=85 c 100 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operating ranges at ta = -40 to +85 c, v ss = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd v dd 4.5 6.0 v v dd 1 v dd 1 2/3v dd v dd input voltage v dd 2 v dd 2 1/3v dd v dd v v ih 1 ce, cl, di, inh 0.4v dd 6.0 input high-level voltage v ih 2 osc external clock operating mode 0.4v dd v dd v v il 1 ce, cl, di, inh 0 0.2v dd input low-level voltage v il 2 osc external clock operating mode 0 0.2v dd v recommended external resistor for rc oscillation rosc osc rc oscillator operating mode 39 k recommended external capacitor for rc oscillation cosc osc rc oscillator operating mode 1000 pf guaranteed range of rc oscillation fosc osc rc oscillator operating mode 19 38 76 khz external clock operating frequency f ck osc external clock operating mode [figure 4] 19 38 76 khz external clock duty cycle d ck osc external clock operating mode [figure 4] 30 50 70 % data setup time tds cl, di [figure 2][figure 3] 160 ns data hold time tdh cl, di [figure 2][figure 3] 160 ns ce wait time tcp ce, cl [figure 2][figure 3] 160 ns ce setup time tcs ce, cl [figure 2][figure 3] 160 ns ce hold time tch ce, cl [figure 2][figure 3] 160 ns high-level clock pulse width t h cl [figure 2][figure 3] 160 ns low-level clock pulse width t l cl [figure 2][figure 3] 160 ns rise time tr ce, cl, di [figure 2][figure 3] 160 ns fall time tf ce, cl, di [figure 2][figure 3] 160 ns inh switching time tc inh , ce [figure 5] 10 s stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lc75836w no.a0428-3/18 electrical characteristics for the allowable operating ranges ratings parameter symbol pin conditions min typ max unit hysteresis v h ce, cl, di, inh 0.03v dd v i ih 1 ce, cl, di, inh v i = 6.0v 5.0 input high-level current i ih 2 osc v i = v dd external clock operating mode 5.0 a i il 1 ce, cl, di, inh v i = 0v -5.0 input low-level current i il 2 osc v i = 0v external clock operating mode -5.0 a v oh 1 s1 to s35 i o = -20 a v dd -0.9 v oh 2 com1 to com4 i o = -100 a v dd -0.9 output high-level voltage v oh 3 p1 to p4 i o = -1ma v dd -0.9 v v ol 1 s1 to s35 i o = 20 a 0.9 v ol 2 com1 to com4 i o = 100 a 0.9 output low-level voltage v ol 3 p1 to p4 i o =1ma 0.9 v v mid 1 s1 to s35 1/3 bias i o = 20 a 2/3v dd -0.9 2/3v dd +0.9 v mid 2 s1 to s35 1/3 bias i o = 20 a 1/3v dd -0.9 1/3v dd +0.9 v mid 3 com1 to com4 1/3 bias i o = 100 a 2/3v dd -0.9 2/3v dd +0.9 output middle-level voltage *1 v mid 4 com1 to com4 1/3 bias i o = 100 a 1/3v dd -0.9 1/3v dd +0.9 v oscillator frequency fosc osc rc oscillator operating mode rosc = 39 k , cosc = 1000pf 30.4 38 45.6 khz i dd 1 v dd power-saving mode 5 i dd 2 v dd v dd = 6.0v output open rc oscillator operating mode fosc = 38khz 350 700 current drain i dd 3 v dd v dd = 6.0v output open external clock operating mode f ck = 38khz v ih 2 = 0.5v dd v il 2 = 0.1v dd 450 900 a note: * 1 excluding the bias voltage generation divider resistors built in the v dd 1 and v dd 2. (see figure 1.) figure 1 v ss to the common and segment drivers v dd 2 v dd 1 except these resistors. v dd
lc75836w no.a0428-4/18 1. when cl is stopped at the low level figure 2 2. when cl is stopped at the high level figure 3 3. osc pin clock timing in external clock operating mode figure 4 osc t ck l t ck h f ck = 1 t ck h+ t ck l [khz] d ck = t ck h t ck h+ t ck l 100[%] v il 2 50% v ih 2 tds v il 1 v il 1 v il 1 v ih 1 50% v ih 1 v ih 1 tch tcs tcp tdh tr tf t tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t
lc75836w no.a0428-5/18 package dimensions unit : mm (typ) 3163b pin assignment com1 com2 com4 s23 s24 com3 s22 s21 s20 s35 v dd v dd 1 v dd 2 lc75836w v ss osc inh ce cl 36 25 37 24 13 12 1 48 di s33 s34 s30 s31 s32 s26 s27 s25 s11 s12 s28 s29 s19 s18 s17 s16 s15 s14 s13 s7 s8 s9 s10 s5 s6 p3/s3 p4/s4 p1/s1 p2/s2 top view 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 sanyo : sqfp48(7x7)
lc75836w no.a0428-6/18 block diagram s1/p1 s2/p2 s3/p3 s5 ce cl di com4 com3 com2 com1 v ss v dd 2 v dd 1 v dd inh osc shift register segment driver & latch ccb interface clock generator common driver s35 control register s4/p4
lc75836w no.a0428-7/18 pin functions symbol pin no. function active i/o handling when unused s1/p1 to s4/p4 s5 to s34 s35 1 to 4 5 to 34 39 segment outputs for displaying the display dat a transferred by serial data input. the s1/p1 to s4/p4 pins can be used as general-purpose output ports when so set up by the control data. - o open com1 to com4 35 to 38 common driver outputs. the fram e frequency is fo [hz]. - o open osc 44 oscillator connection. an oscillator circ uit is formed by connecting an external resistor and capacitor to this pin. this pin can be used as the external clock input pin if external clock operating mode is selected with the control data. - i/o v dd ce cl di 46 47 48 serial data transfer inputs. must be connected to the controller. ce: chip enable cl: synchronization clock di: transfer data h - i i i gnd inh 45 display off control input ? inh = low (v ss ) ...display forced off s1/p1 to s4/p4 = low (v ss ) (these pins are forcibly set to t he segment output port function and held at the v ss level.) s5 to s35 = low (v ss ) com1 to com4 = low (v ss ) osc = z (high impedance) rc oscillation stopped inhibits external clock input. ? inh = high (v dd )...display on rc oscillation enabled (rc oscillator operating mode) enables external clock input (external clock operating mode). however, serial data transfer is possible when the display is forced off. l i gnd v dd 1 41 used to apply the lcd drive 2/3 bias voltage externally. - i open v dd 2 42 used to apply the lcd drive 1/3 bias voltage externally. - i open v dd 40 power supply pin. a power voltage of 4.5 to 6.0v must be applied to this pin. - - - v ss 43 ground pin. must be connected to ground. - - -
lc75836w no.a0428-8/18 serial data transfer formats 1. when cl is stopped at the low level note: dd is the direction data. 0 d135 b1 b0 1 0 d110 d109 0 dd 2 bit fixed data 14 bit ccb address 8 bit 0 0 0 0 1 0 1 b3 b2 a1 a0 a3 a2 d136 0 000 01 01 0 0 0 0 0 display data 32 bit d140 d139 d138 d137 d134 d133 d132 d131 b1 b0 d2 d1 1 0 d26 0 dd 2 bit control data 10 bit display data 36 bit ccb address 8 bit di cl ce 0 0 0 d29 1 0 1 b3 b2 a1 a0 a3 a2 d27 d31 d30 d32 sc oc p2 p1 0 0 bu p0 fc0 fc1 fc2 d28 d23 d24 d25 d36 d35 d34 d33 b1 b0 1 0 d38 d37 0 dd 2 bit fixed data 10 bit display data 36 bit ccb address 8 bit 0 0 0 d68 1 0 1 b3 b2 a1 a0 a3 a2 d64 d63 01 00 0 0 00 0 0 0 d65 d67 d66 d61 d62 d59 d60 d72 d71 d70 d69 0 b1 b0 1 0 d74 d73 0 dd 2 bit fixed data 10 bit display data 36 bit ccb address 8 bit 0 0 0 1 0 1 b3 b2 a1 a0 a3 a2 d96 d95 0 00 01 0 0 0 0 0 d104 d103 d102 d101 d100 d99 d98 d97 d108 d107 d106 d105
lc75836w no.a0428-9/18 2. when cl is stopped at the high level note: dd is the direction data. ? ccb address ....... "46h" ? d1 to d140 ......... display data ? fc0 to fc2 ......... common/segment output waveform frame frequency control data ? p0 to p2 .............. segment output port/gener al-purpose output port switching control data ? oc ................ ...... rc oscillator operating mode/external cl ock operating mode switching control data ? sc ...................... segments on/off control data ? bu ...................... normal mode/power-saving mode control data fc0 sc b1 b0 d2 d1 0 0 0 1 0 d29 d24 d23 dd 2 bit control data 10 bit display data 36 bit ccb address 8 bit di cl ce b3 b2 a1 a0 a3 a2 1 0 1 d26 d25 d28 d27 d31 d30 d32 0 d36 d35 d34 p1 p0 p2 bu 0 0 d33 oc fc1 fc2 0 b1 b0 0 0 0 1 0 0 d136 d110 d109 d135 dd 2 bit fixed data 14 bit display data 32 bit ccb address 8 bit b3 b2 a1 a0 a3 a2 1 0 1 0 000 01 1 00 0 0 0 0 0 d140 d139 d138 d137 d134 d133 d132 d131 0 b1 b0 0 0 0 1 0 d60 d38 d37 dd 2 bit fixed data 10 bit display data 36 bit ccb address 8 bit b3 b2 a1 a0 a3 a2 1 0 1 0 01 0 d64 d63 d62 d61 00 0 0 0 0 0 d59 d65 d66 d67 d68 d69 d70 d71 d72 0 b1 b0 0 0 0 1 0 d96 d74 d73 d95 dd 2 bit fixed data 10 bit display data 36 bit ccb address 8 bit b3 b2 a1 a0 a3 a2 1 0 1 0 00 1 00 0 0 0 0 0 d97 d98 d99 d100 d101 d102 d103 d104 d108 d107 d106 d105
lc75836w no.a0428-10/18 serial data transfer example ? when 109 or more segments are used all 192 bits of serial data must be sent. ? when fewer than 109 segments are used either 48, 96, or 144 bits of serial data must be sent, depending on the number of segments to be used. however, the serial data shown below (the d1 to d36 display data and the control data) must always be sent. 48 bit 8 bit d2 d 1 d23 d73 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d24 d25 d26 d27 fc0 0 p0 p1 p2 fc1 fc2 oc sc bu 00 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d37 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d74 d38 d59 d60 d61 d62 d95 d96 0000 0 0 0 0 0 0 0 1 0000 0 0 0 0 0 0 0 1 d31 d63 d64 d109 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d110 d131 d136 00000000 0 0 0 0 0 0 1 1 d97 d98 d99 d100 d140 d139 d138 d137 d135 d134 d133 d132 d36 d30 d29 d28 d68 d67 d66 d65 d104 d103 d102 d101 d32 d35 d34 d33 d72 d71 d70 d69 d108 d107 d106 d105 48 bit 8 bit d2 d1 d23 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d24 d25 d26 d27 fc0 0 p0 p1 p2 fc1 fc2 oc sc bu 00 d28 d32 d31 d30 d29 d36 d35 d34 d33
lc75836w no.a0428-11/18 control data functions 1. fc0 to fc2: common/segment output waveform frame frequency control data these control data bits set the frame frequency of the common and segment output waveforms. control data fc0 fc1 fc2 frame frequency fo [hz] 1 1 0 fosc/768,f ck /768 1 1 1 fosc/576,f ck /576 0 0 0 fosc/384,f ck /384 0 0 1 fosc/288,f ck /288 0 1 0 fosc/192,f ck /192 2. p0 to p2: segment output port/general-purpose output port switching control data these control data bits switch the segment output port/general-purpose output port functions of the s1/p1 to s4/p4 output pins. control data output pin state p0 p1 p2 s1/p1 s2/p2 s3/p3 s4/p4 0 0 0 s1 s2 s3 s4 0 0 1 p1 s2 s3 s4 0 1 0 p1 p2 s3 s4 0 1 1 p1 p2 p3 s4 1 0 0 p1 p2 p3 p4 note: sn (n = 1 to 4): segment output ports pn (n = 1 to 4): general-purpose output ports note that when the general-purpose output port function is selected, the correspondence between the output pins and the display data will be that shown in the table. output pin corresponding display data s1/p1 d1 s2/p2 d5 s3/p3 d9 s4/p4 d13 for example, if the general-purpose output port function is selected for the s4/p4 output pin, that output pin will output a high level (v dd ) when the display data d13 is 1, and a low level (v ss ) when the d13 is 0. 3. oc: rc oscillator operating mode/external clock operating mode switching control data. this control data bit switches the osc pin function (either rc oscillator operating mode or external clock operating mode). oc osc pin function 0 rc oscillator operating mode 1 external clock operating mode note: an external resistor, rosc, and an external capacitor, cosc, must be conn ected to the osc pin if rc oscillator operating mode is selected. 4. sc: segment on/off control data this control data bit controls the on/off state of the segments. sc display state 0 on 1 off note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins.
lc75836w no.a0428-12/18 5. bu: normal mode/power-saving mode control data this control data bit selects either normal mode or power saving mode. bu mode 0 normal mode 1 power saving mode. in rc oscillator operating mode (oc = 0), the osc pin o scillator is stopped, and in external clock operating mode (oc = 1), acceptance of the external clock is stopped. in this mode the common and segm ent output pins go to the v ss levels. however, s1/p1 to s4/p4 output pins that are se t to be general-purpose output ports by the control data p0 to p2 can be used as general-purpose output ports.
lc75836w no.a0428-13/18 display data and output pin correspondence output pin com1 com2 com3 com4 output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 s19 d73 d74 d75 d76 s2/p2 d5 d6 d7 d8 s20 d77 d78 d79 d80 s3/p3 d9 d10 d11 d12 s21 d81 d82 d83 d84 s4/p4 d13 d14 d15 d16 s22 d85 d86 d87 d88 s5 d17 d18 d19 d20 s23 d89 d90 d91 d92 s6 d21 d22 d23 d24 s24 d93 d94 d95 d96 s7 d25 d26 d27 d28 s25 d97 d98 d99 d100 s8 d29 d30 d31 d32 s26 d101 d102 d103 d104 s9 d33 d34 d35 d36 s27 d105 d106 d107 d108 s10 d37 d38 d39 d40 s28 d109 d110 d111 d112 s11 d41 d42 d43 d44 s29 d113 d114 d115 d116 s12 d45 d46 d47 d48 s30 d117 d118 d119 d120 s13 d49 d50 d51 d52 s31 d121 d122 d123 d124 s14 d53 d54 d55 d56 s32 d125 d126 d127 d128 s15 d57 d58 d59 d60 s33 d129 d130 d131 d132 s16 d61 d62 d63 d64 s34 d133 d134 d135 d136 s17 d65 d66 d67 d68 s35 d137 d138 d139 d140 s18 d69 d70 d71 d72 note: applies when the s1/p1 to s4/p4 output pins are set to their segment output function. for example, the table below lists the output states for the s21 output pin. display data d81 d82 d83 d84 output pin (s21) state 0 0 0 0 the lcd segments corresponding to com1, com2, com3, and com4 are off. 0 0 0 1 the lcd segment corresponding to com4 is on. 0 0 1 0 the lcd segment corresponding to com3 is on. 0 0 1 1 the lcd segments corresponding to com3 and com4 are on. 0 1 0 0 the lcd segment corresponding to com2 is on. 0 1 0 1 the lcd segments corresponding to com2 and com4 are on. 0 1 1 0 the lcd segments corresponding to com2 and com3 are on. 0 1 1 1 the lcd segments corresponding to com2, com3, and com4 are on. 1 0 0 0 the lcd segment corresponding to com1 is on. 1 0 0 1 the lcd segments corresponding to com1 and com4 are on. 1 0 1 0 the lcd segments corresponding to com1 and com3 are on. 1 0 1 1 the lcd segments corresponding to com1, com3, and com4 are on. 1 1 0 0 the lcd segments corresponding to com1 and com2 are on. 1 1 0 1 the lcd segments corresponding to com1, com2, and com4 are on. 1 1 1 0 the lcd segments corresponding to com1, com2, and com3 are on. 1 1 1 1 the lcd segments corresponding to com1, com2, com3, and com4 are on.
lc75836w no.a0428-14/18 output waveforms (1/4-duty 1/3-bias drive scheme) control data fc0 fc1 fc2 frame frequency fo [hz] 1 1 0 fosc/768,f ck /768 1 1 1 fosc/576,f ck /576 0 0 0 fosc/384,f ck /384 0 0 1 fosc/288,f ck /288 0 1 0 fosc/192,f ck /192 v dd 1 v dd 2 fo[hz] v dd com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are on. lcd driver output when lcd segments corresponding to com2, and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are off. 0v v dd 1 v dd 2 v dd 0v v dd 1 vd d 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v v dd 1 v dd 2 v dd 0v
lc75836w no.a0428-15/18 display control and the inh pin since the lsi internal data (the display data d1 to d140 an d the control data) is undefined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display. (this sets the s1/p1 to s4/p4, s5 to s35, and com1 to com4 pins to the v ss level.) and during this period send serial data from the controller. the controller should then set the inh pin high after the data transfer has completed. this procedure prevents meaningless displays at power on. (see figure 5.) figure 5 notes: t1>0 tc ??? 10 s min display data and control data dtratransterred v dd t1 d1 to d36, internal data fc0 to fc2, p0 to p2, oc, sc, bu internal data (d37 to d72) internal data (d73 to d108) undefined undefined ce inh undefined undefined defined defined defined defined undefined undefined undefined undefined v il 1 tc v il 1 internal data (d109 to d140)
lc75836w no.a0428-16/18 notes on controller transf er of display data since the lc75836w transfer the display data (d1 to d140) in four separate transfer operations, we recommend that applications make a point of completing all four data transfers within a period of less than 30ms to prevent observable degradation of display quality. osc pin peripheral circuit (1) rc oscillator operating mode (control data oc = 0) an external resistor, rosc, and an ex ternal capacitor, cosc, must be connected between the osc pin and gnd if rc oscillator operating mode is selected. (2) external clock operating mode (control data oc = 1) when the external clock operating m ode is selected, insert a current pr otection resistor rg (4.7 to 47k ) between the osc pin and external clock output pin (external oscillato r). determine the value of the resistance according to the allowable current value at the external clock output pin. also make sure that the waveform of the external clock is not heavily distorted. note: allowable current value at external clock output pin > v dd rg osc external clock output pin rg external oscillator osc cosc rosc
lc75836w no.a0428-17/18 sample application circuit 1 1/4 duty, 1/3 bias (for use with normal panels) * 2: the pins to be connected to the controller (ce, cl, di, inh ) can handle 3v. * 3: in rc oscillator operating mode, an external resistor, ro sc, and an external capacito r, cosc, must be connected between the osc pin and ground. if external clock operating mode is selected, a current protection resistor, rg (4.7 to 47 k ), must be inserted between the external clock output pin (on the external oscillator) and the osc pin. (see the ?osc pin peripheral circuit? section.) * 4: when a capacitor except the recommended external capac itance (cosc = 1000pf) is co nnected to the osc pin, it should be in the range 220 to 2200pf. sample application circuit 2 1/4 duty, 1/3 bias (for use with large panels) * 2: the pins to be connected to the controller (ce, cl, di, inh ) can handle 3v. * 3: in rc oscillator operating mode, an external resistor, ro sc, and an external capacito r, cosc, must be connected between the osc pin and ground. if external clock operating mode is selected, a current protection resistor, rg (4.7 to 47 k ), must be inserted between the external clock output pin (on the external oscillator) and the osc pin. (see the ?osc pin peripheral circuit? section.) * 4: when a capacitor except the recommended external capac itance (cosc = 1000pf) is co nnected to the osc pin, it should be in the range 220 to 2200pf. general-purpose output ports (p4) (p2) (p1) di cl ce inh v dd 1 s35 com4 s34 s5 p4/s4 p2/s2 p1/s1 com3 com2 com1 *2 v dd v dd 2 v ss c from the controller +5v c (p3) p3/s3 *4 osc *3 used for functions such as backlight control lcd panel (up to 140 segments) c 0.047 ? r 1k c 0.047 f lcd panel (up to 140 segments)
lc75836w no.a0428-18/18 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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